The flow of data, known in the art as traffic, in an asynchronous transfer mode (ATM) network consists of ATM cells which are fixed-sized packets of 53 bytes that are transferred between ATM endnodes in the ATM network. In an ATM endnode, ATM cells are generated from user data by an ATM layer and transmitted over the ATM network by the PHY layer (as defined by the ISO standard). Typically, a simple interface is used to transfer ATM cells generated by the ATM layer to a first-in first-out (FIFO) queue in the PHY layer. One exemplary interface is an industry standard interface referred to as UTOPIA, i.e., the Universal Test and Operations PHY Interface for ATM. The UTOPIA specification, incorporated herein, defines the interface between the ATM layer and the PHY layer that is used to transfer ATM cells from the ATM layer to the PHY layer.
The UTOPIA specification (Level 1, Version 2.01 - Mar. 21, 1994) describes the interface as an "8-bit wide datapath, operating up to 25 MHz using either an octet-level or cell-level flow control." Two signals called TxFull*/TxClav and TxEnb* are used to implement the flow control in the transmit portion of the UTOPIA specification. TxEnb* is an active low signal asserted by the ATM layer during cycles when valid ATM cell data is being transferred. TxFull*/TxClav has different meanings depending upon the type of flow control being used.
For octet-level flow control, TxFull* is an active low signal from the PHY layer to the ATM layer, asserted by the PHY layer to indicate that the FIFO of the PHY layer can accept at most four more bytes of data. For cell-level flow control, TxClav is an active high signal from the PHY layer to the ATM layer, that is asserted by the PHY layer to indicate it can accept the transfer of a complete ATM cell. The PHY layer will deassert TxClav at least four bytes before the end of an ATM cell if it cannot accept the immediate transfer of the subsequent ATM cell.
If the ATM layer has user data to transmit, it will begin to generate ATM cells and transfer these ATM cells to the PHY layer while space is available in the FIFO of the PHY layer. Most PHY layer implementations will not remove an ATM cell from their FIFO for transmission onto the ATM network until the entire ATM cell is present in the FIFO. In order to ensure that the entire bandwidth of the ATM network can be utilized, most ATM layers are able to generate and transfer ATM cells to the PHY layer faster than the PHY layer can transmit these ATM cells onto the network. With constant data traffic, the FIFO of the PHY layer will eventually fill up with N ATM cells, where N is the size of the FIFO in ATM cells. ATM cells that are transferred from the ATM layer to the PHY layer when the FIFO of the PHY layer is full or nearly full will sit in the FIFO of the PHY layer for (N-1) ATM cell times before they can be transmitted onto the ATM network. The flow control mechanism of the UTOPIA specification will only prevent overflowing the FIFO of the PHY layer. The UTOPIA specification does not provide a mechanism to allow the ATM layer to keep the FIFO of the PHY layer as empty as possible or to permit the ATM layer to synchronize itself to the ATM network.
A mechanism to control the latency experienced by an ATM cell before transmission out onto the ATM network is needed, as well as a means to allow the ATM layer to suspend the transfer of ATM cells to the PHY layer when the FIFO of the PHY layer is nearly full or full with N ATM cells in order to permit the removal of a programmable number of bytes from the FIFO. In addition, a means to synchronize the ATM layer to the ATM network is needed.